SATH: Simulated Annealing C code To FPGA Hardware compiler
Customizing Pipelined Simulated Annealing IP cores with a dedicated C to FPGA compiler
Autor:
Jonathan Phillips
Dostupnosť:
U vydavateľa na objednávku
Odosielame za 17-27 dní
58.19
€
A tool flow is presented for deriving accelerator§circuits on an FPGA §from ANSI C source code by ex...
