Kniha Efficient Test Data Compression and Fault Analysis in VLSI Circuits Sivaganesan Subramaniam

Efficient Test Data Compression and Fault Analysis in VLSI Circuits

Jazyk: Angličtina
Väzba: Brožovaná
Vydavateľ: Scholars' Press
Dostupnosť: Skladom u dodávateľa
Odosielame za 5-8 dní
39.62
In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volu...

Informácie o knihe

Jazyk
Angličtina
Väzba
Kniha - Brožovaná
Vydalo
2019
Stránok
84
EAN
9786138834304
ISBN
6138834305
Enbook ID
22601189
Vydavateľ
Hmotnosť
136
Rozmery
152 x 229 x 5

Kompletný popis

In higher order SOC (System On Chip) circuit, designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requirements, but also an increase in testing time. Test data compression addresses this problem by reducing the test data volume without affecting the overall system performance. In this, testable input data (test data) is generated by using Automatic test pattern generation (ATPG) then it is compressed and compressed data stored to memory. To test the particular circuit that time we will decompress the stored memory test data and then decompressed test data given to the Design Under Test (DUT). Finally DUT fault is tested and identified. It proposes a test compression technique using efficient dictionary selection and bitmask method to significantly reduce the testing time and memory requirements. This algorithm giving a best possible test compression of 92% when compared with other compression methods.

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