Development of Efficient Hardware Architecture for Image Compression

Name: Development of Efficient Hardware Architecture for Image Compression
Brand: LAP Lambert Academic Publishing
SKU: 9786202197526
Price: 64.65 EUR
Availability: InStock

The Mapping of the Computational Tasks Associated with the Discrete Wavelet Transform DWT

Autor: Khamees Khalaf Hasan Al-jumaily

Jazyk:

Väzba: Brožovaná

Vydavateľ: LAP Lambert Academic Publishing

Dostupnosť: Skladom u dodávateľa

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Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design...

Informácie o knihe

Autor

Khamees Khalaf Hasan Al-jumaily

Jazyk

Angličtina

Väzba

Kniha - Brožovaná

Vydalo

2017

Stránok

268

EAN

9786202197526

Enbook ID

18795645

Vydavateľ

LAP Lambert Academic Publishing

Hmotnosť

417

Rozmery

150 x 220 x 16

Kompletný popis

Focusing on the intensive computations involved in the discrete wavelet transform (DWT), the design of efficient hardware architectures for a fast computation of the transform has become imperative, especially for real-time applications. With this overall objective, the mapping of the computational tasks associated with the various resolution levels of the 5/3 DWT is first mathematically modeled, and then a modified computation of the DWT stages are explored from the standpoint of evading computing high frequency subbands. Furthermore, a Haar wavelet transform (HWT) is used for comparison. The proposed forward DWT (FDWT) and its inverse DWT (IDWT) hardware architecture filter generated similar results compared to the MATLAB model for the seven levels of DWT decomposition. Simulations were performed using grayscale images of different sizes to validate the proposed design and attain speed performance appropriate for a number of real-time applications.

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Development of Efficient Hardware Architecture for Image Compression

The Mapping of the Computational Tasks Associated with the Discrete Wavelet Transform DWT

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Kompletný popis

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