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Design and Implementation of a Multicore Processor Using FPGA

Name: Design and Implementation of a Multicore Processor Using FPGA
Brand: LAP Lambert Academic Publishing
SKU: 9783330073845
Price: 60.26 EUR
Availability: InStock

Autor: Ali J. Ibada

Jazyk:

Väzba: Brožovaná

Vydavateľ: LAP Lambert Academic Publishing

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This book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS pro...

Informácie o knihe

Autor

Ali J. Ibada

Jazyk

Angličtina

Väzba

Kniha - Brožovaná

Vydalo

2017

Stránok

212

EAN

9783330073845

Enbook ID

16335951

Vydavateľ

LAP Lambert Academic Publishing

Hmotnosť

334

Rozmery

150 x 220 x 13

Kompletný popis

This book presents a study of multicore RISC processor by using FPGA. A 32-bit single cycle MIPS processor is designed using VHDL, which can execute 50 instructions. To reach parallel processing by exploiting Instruction Level Parallelism (ILP), two-way superscalar MIPS processor is designed by duplicating some components of single cycle MIPS processor and added hazard unit. Then, the single cycle MIPS processor subdivided to five pipeline stages 5-stages to obtain pipelined MIPS processor. To increase processor performance memory hierarchy is exploited by adding cache memory to pipeline MIPS processor. A Multicore MIPS processor is achieved by connecting two of complete single core together; these cores operate as separate independent processors within a single chip. Coherency problems are solved by using MESI protocol. All processors are designed using Xilinx ISE 13.4 Design Suite. The entire processor design is configured on a Xilinx Spartan-3AN FPGA starter kit, and the results have been displayed on the 2×16 LCD internal screen of the kit and external VGA screen.

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Design and Implementation of a Multicore Processor Using FPGA

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