Practical Guide for SystemVerilog Assertions

Name: Practical Guide for SystemVerilog Assertions
Brand: Springer-Verlag New York Inc.
SKU: 9781489992796
Price: 162.98 EUR
Availability: InStock

Autor: Meyyappan Ramanathan

Jazyk:

Väzba: Brožovaná

Vydavateľ: Springer-Verlag New York Inc.

Dostupnosť: Skladom u dodávateľa v malom množstve

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162.98 €

SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench....

Informácie o knihe

Autor

Meyyappan Ramanathan

Jazyk

Angličtina

Väzba

Kniha - Brožovaná

Vydalo

2014

Stránok

334

EAN

9781489992796

ISBN

9781489992796

Enbook ID

09165443

Vydavateľ

Springer-Verlag New York Inc.

Hmotnosť

551

Rozmery

155 x 235 x 17

Kompletný popis

SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process. Engineers are used to writing testbenches in verilog that help verify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides the engineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.§

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Practical Guide for SystemVerilog Assertions

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