A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures

Name: A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures
Brand: Springer Netherlands
SKU: 9780306477430
Price: 100.0 EUR
Availability: InStock

Autor: Ian N. Dunn, Gerard G.L. Meyer

Jazyk:

Väzba: Pevná

Vydavateľ: Springer Netherlands

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Despite five decades of research, parallel computing remains an exotic, frontier technology on the f...

Informácie o knihe

Autor

Ian N. Dunn, Gerard G.L. Meyer

Jazyk

Angličtina

Väzba

Kniha - Pevná

Vydalo

2003

Stránok

108

EAN

9780306477430

ISBN

0306477432

Enbook ID

01379612

Vydavateľ

Springer Netherlands

Hmotnosť

363

Rozmery

155 x 235 x 13

Kompletný popis

Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment. To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents three case studies requiring various degrees of optimization for parallel execution.

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A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures

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